1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, it relates to an improvement in a transistor extracting portion in a bipolar semiconductor integrated circuit device
2. Description of the Prior Art
In general, a transistor of a bipolar semiconductor integrated circuit device is formed in an electrically isolated island by p-n junction/isolation, oxide film isolation employing a selective oxidization process or a method employing triple diffusion. Such a semiconductor device is well known in the art by U.S. Pat. No. 4,445,268 entitled "Method of Manufacturing a Semiconductor Integrated Circuit BI-MOS Device" granted to Hirao. Further, technique of forming an oxide film only in a region around a polysilicon portion of a polysilicon emitter is disclosed in "Subnanosecond Self-Aligned I.sup.2 L/MTL Circuits", IEEE Transactions on Electron Device Vol. ED-27 No. Aug. 8, 1980, pp. 1379.
FIGS. 1A to 1E are cross-sectional views showing principal steps of a conventional method of manufacturing a semiconductor device. The conventional method of manufacturing a semiconductor device is now described with reference to these drawings An n.sup.+ -type layer 2 of high impurity concentration for implementing a collector buried layer is selectively formed on a p.sup.- -type silicon substrate 1 of low impurity concentration, followed by growth of an n.sup.- -type epitaxial layer 3 thereon (FIG. 1A).
Then the substance is selectively oxidized by utilizing a nitride film 201 formed on a pad oxide film 101 as a mask, whereby a thick isolation oxide film 102 is formed while a p-type layer 4 is simultaneously formed under the isolation oxide film 102 for cutting a channel (FIG. 1B).
The nitride film 201 employed as a mask for the aforementioned selective oxidization is then removed with the pad oxide film 101 to newly form an oxide film 103 for protecting the substance from ion implantation, thereby to form a p.sup.+ -type layer 5 for implementing an external base layer by employing a photoresist film (not shown in this stage) as a mask. Thereafter the photoresist film is removed to newly form a photoresist film 301, which is employed as a mask for forming a p-type layer 6 for implementing an active base layer by ion implantation (FIG. 1C).
The photoresist film 301 is then removed and the substance is covered by a passivation film 401 generally made of phos-silicate glass (PSG) and subjected to heat treatment for annealing the base ion implantation layers 5 and 6 as well as densificating the PSG film 401 to form an external base layer 51 and an active base film 61 in an intermediate stage, followed by formation of holes 70 and 80 in the PSG film 401 to form an n.sup.+ -type layer 7 for implementing an emitter layer and an n.sup.+ -type layer 8 for implementing a collector electrode extracting layer by ion implantation (FIG. 1D).
Thereafter the respective ion implantation layers are annealed to completely implement an external base layer 52 and an active base layer 62 and form an emitter layer 71 and a collector electrode extracting layer 81, followed by formation of a hole 50 for extracting the base electrode. Then the respective holes 50, 70 and 80 are provided with films 501 of metal silicide such as platinum silicide (Pt-Si) and palladium silicide (Pd-Si) for preventing junction-spike of the electrodes, followed by formation of a base electrode wire 9, an emitter electrode wire 10 and a collector electrode wire 11 by low-resistance metal such as aluminum (A1) (FIG. 1E).
FIGS. 2, 3A and 3B are plan views showing patterns of conventional transistors manufactured by the above conventional method. FIG. 2 shows single-base structure which corresponds to FIG. 1E and FIG. 3A shows double-base structure while FIG. 3B shows multi-emitter structure.
Generally, the frequency characteristic of a transistor depends on the base-to-collector capacity and the base resistance etc., which must be decreased for improving the frequency characteristic. The p.sup.+ -type external base layer 52 is provided for lowering the base resistance in the aforementioned structure, whereas provision of the same leads to increase in the base-to-collector capacity. Further, the base resistance depends on a distance D.sub.1 between the emitter layer 71 and the base electrode extracting hole 50, i.e., the total of the distance between the base electrode wire 9 and the emitter electrode wire 10 and the length of margins of the respective electrode wires 9 and 10 extending over the respective holes 50 and 70, and such margins inevitably remain even if the distance between the electrode wires 9 and 10 is reduced by improving accuracy of photoetching. Further, the transistor may be brought in the double-base structure as shown in FIG. 3A for reducing the base resistance, as is well known in the art. In this case, the emitter length L.sub.2 as shown in FIG. 3A may be slightly smaller than the emitter length L.sub.1 as shown in FIG. 2 since only the edge portion of the emitter opposite to the base electrode may be moved in high-current/high-frequency operation. However, the base area is extremely increased in the double-base structure. Further, the base wiring region is also increased.
As well known in the art, further, the transistor may be brought in the multi-emitter structure as shown in FIG. 3B for reducing the base resistance while improving the current driving ability. In this case, the emitter length L.sub.3 as shown in FIG. 3B may be slightly smaller than the emitter length L.sub.1 as shown in FIG. 2, since only the edge portions of the emitters opposite to the base electrode may be moved in high-current/high-frequency operation. However, the base area is extremely increased in the multi-emitter structure since provision of a base electrode is required between the emitters. Further, the base wiring region is also increased.